1. Field of the Invention
The present invention relates to a switching circuit and a switched capacitor filter fabricated by a complementary metal oxide semiconductor (CMOS) fabrication process that are widely applied to various semiconductor applications, and, more particularly, to a switching circuit and a switched capacitor filter that are operable under a lower voltage, or a low driving voltage and have a low power consumption.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional switched capacitor filter having a basic configuration that has been disclosed by Japanese patent laid-open publication number JP-A-4/138712 and the like. In FIG. 1, the reference character 24 designates an input terminal of the switched capacitor filter to which an input signal is inputted. The reference number 28 denotes an operational amplifier having an inverting input terminal and a non-inverting input terminal. The inverting input terminal receives the input signal transferred from the input terminal 1 and the non-inverting terminal is connected to a ground, namely is grounded. This operational amplifier outputs an inverted amplified signal whose amplitude corresponds to a voltage between the inverting input terminal and the non-inverting input terminal. The reference number 30 indicates an output terminal through which the inverted amplified signal is outputted as the output of the switched capacitor filter. The reference number 29 denotes a fixed capacitor located between the non-inverting input terminal of the operational amplifier 28 and the output terminal 30 in parallel with the operational amplifier 28. The input signal is transferred from the input terminal 24 to the output terminal 30 through signal paths, or through signal channels, formed by the components described above. The reference number 53 designates a connection node of the input side through which the fixed capacitor 29 is connected to the non-inverting input terminal of the operational amplifier 28. The reference number 54 designates a connection node of the output side of the operational amplifier through which the fixed capacitor 29 is connected to the output terminal of the operational amplifier 28.
The reference number 26 designates an input capacitor placed between the connection node 53 of the input side and the input terminal 24. The reference number 25 denotes a first switching circuit, located between the input capacitor 26 and the input terminal 24, for switching the connection between the input capacitor 26 and the input terminal 24 or the ground side of the ground voltage. The reference number 27 designates a second switching circuit, placed between the input capacitor 26 and the connection node 53 of the input side, for switching the connection between the input capacitor 26 and the connection node 53 of the input side or the ground side of the ground voltage.
The reference number 32 denotes a limit capacitor placed between the connection node 53 of the input side and the connection node 54 of the output side.
The reference number 31 designates a third switching circuit, placed between the limit capacitor 32 and the connection node 53 in the input side, for switching the connection between the limit capacitor 32 and the connection node 53 in the input side or the ground side of the ground voltage.
The reference number 33 denotes a fourth switching circuit, located between the limit capacitor 32 and the connection node 54 of the output side, for switching the connection between the limit capacitor 32 and the connection node 54 of the output side or the ground side of the ground voltage. The reference number 1 designates an input terminal to which a switching signal is inputted. The reference number 2 denotes a control inverter for inverting the level of the switching control signal and for outputting the inverted switching control signal having the inverted phase. In the conventional switched capacitor filter having the above configuration, the switching control signal and the inverted switching signal are inputted directly to the switching circuits 25, 27, 31, and 33.
Next, a description will be given of the operation of the conventional switched capacitor filter shown in FIG. 1.
Hereinafter, each of the switching circuits 25, 27, 31, and 33 connects each of the capacitors 26 and 32 to the signal paths of the input signal while the level of the switching control signal is the high level, and each connects each of the capacitors 26 and 32 to the ground voltage while the level of the switching control signal is the low level, where the signal path is formed through the input terminal 24, the connection node of the input side, and the connection node 54 of the output side.
First, when the level of the switching control signal is a level of a low voltage (or a low level), all of the switching circuits 25, 27, 31, and 33 perform so that the input capacitor 26 and the limit capacitor 32 are connected to the level of the ground voltage. Thereby, both terminals of each of the input capacitor 16 and the limit capacitor 36 are short-circuited and both capacitors are discharged completely.
Under the above situation, when the level of the switching control signal is changed to a level of a high voltage (or a high level), all of the switching circuits 25, 27, 31, and 33 perform so that the input capacitor 26 and the limit capacitor 32 are connected to the signal path side. Then, a charging current I2 flows through the input capacitor 26. The magnitude of the charging current I2 corresponds to the voltage difference between the input voltage V1 of the input signal and the voltage V2 at the connection node 53 of the input side. The input capacitor 26 is charged to the voltage difference (V1-V2). Similarly, a charging current I3 flows through the limit capacitor 32. The magnitude of the charging current I3 corresponds to the voltage difference between the voltage V2 at the connection node 53 of the input side and the voltage V3 at the connection node 54 of the output side. Limit capacitor 32 is charged to the voltage difference (V2-V3).
Further, when the level of the switching control signal is changed to the low level again, both terminals of each of the input capacitor 16 and the limit capacitor 36 are short-circuited and both capacitors are discharged completely.
Thereby, those two capacitors 26 and 32 act the circuits through which the charging current flows per period of the switching control signal by the switching operation of the switching circuits 25, 27, 31, and 33 connected to both sides of each of the capacitors 26 and 32. Those capacitors 26 and 32 act as a resistance for an input signal whose frequency is adequately lower than the frequency of the switching control signal.
FIG. 2 is a block diagram showing an equivalent circuit of the switched capacitor filter when the frequency of the switching control signal is adequately high when comparing with the input signal. In FIG. 2, the reference number 46 designates an input equivalent resistance as an equivalent circuit of the input capacitor 26. The reference number 47 denotes a limit equivalent circuit as an equivalent circuit of the limit capacitor 32.
Because other components of the equivalent circuit shown in FIG. 1 are equal to the components of the switched capacitor filter shown in FIG. 1, the same reference numbers of them will be used and the explanation of them is omitted here for brevity.
When the capacitance of the input capacitor 26 is C2, and the capacitance of the limit capacitor 32 is C1, and one period of the switching control signal is Ts, the value of the input equivalent resistance becomes Ts/C2, and the value of the limit equivalent resistance becomes Ts/C1.
In the equivalent circuit of the switched capacitor filter described above, the input current I2 flows when the voltage V1 of the input signal is increased, for example. This input current I2 is obtained by dividing the voltage difference between the input voltage V1 and the voltage V2 at the connection node 53 in the input side by the input equivalent resistance 46 (Ts/C2). This input current I2 flows through one terminal of the fixed capacitor 29 and the limit equivalent resistance 47 (Ts/C1), and the fixed capacitor 29 is thereby charged. At this time, electric charges are supplied to the other terminal of the fixed capacitor 29 from the operational amplifier 28. As a result, the voltage V3 having a reverse polarity capable of amplifying the input voltage V1 is outputted to the output terminal 30 according to the charged voltage of the fixed capacitor 29.
Because the conventional switched capacitor filter has the configuration described above, it is required to have a switching circuit to switch the connection nodes to which the capacitor will be connected. Thereby, it is limited or difficult to decrease the voltage of an electric power source as the driving voltage, and it is thereby difficult to reduce the entire voltage of semiconductor integrated circuit devices.
This drawback of the conventional switched capacitor filter will be explained in detail by using a concrete example.
FIG. 3 is a circuit diagram showing a conventional switching circuit. In FIG. 3, the reference number 8 designates one selection connection terminal of the switching circuit, and 9 denotes other selection connection terminal in this switching circuit. The reference number 10 denotes a common terminal that will be selectively connected to one of the selection connection terminals 8 and 9. The reference number 6 designates a forward switching element comprising a P channel electrical field effect transistor (a P channel FET) and a N channel electrical field effect transistor (a N channel FET). Both sources of the P channel FET and the N channel FET in the forward switching element 6 are connected to each other, and the drains of both FETs are connected to each other. The reference number 7 indicates an inverse switching element comprising a P channel FET and a N channel FET. Similar to both the P channel FET 8 and the N channel FET 9 in the forward switching element 6, both sources of the P channel FET and the N channel FET in the inverse switching circuit 7 are connected to each other and the drains of the P-Channel FET and the N-Channel FET are connected to each other. Because other component elements are the same of the components in the switched capacitor filter shown in FIG. 1, the same reference numbers are used, and the explanation of them is omitted here for brevity.
Next, a description will be given of the operation of the conventional switching circuit shown in FIG. 3.
The source electrode of the forward switching element 6 is connected to the selection connection terminal 8 as one of the selection connection terminals 8 and 9. The drain electrode of the forward switching element 6 is connected to the common terminal 10. The source terminal of the inverse switching element 7 is connected to the selection connection terminal 9, and the drain electrode is connected to the common terminal 10. In addition, the gate electrode of the P channel FET in the forward switching element 6 inputs an inverted switching control signal, and the gate electrode of the N channel FET in the forward switching element 6 inputs a switching control signal, the gate electrode of the P channel FET in the inverse switching element 7 inputs the switching control signal, and the gate electrode of the N channel FET in the inverse switching element 7 inputs the inverted switching control signal.
Next, a description will be given of the operation of the conventional switching circuit shown in FIG. 3.
When the level of the switching control signal is a level of a high voltage (an H level), the gate electrode of the N channel FET in the forward switching element 6 inputs the signal of the H level and the gate electrode of the P channel FET in the forward switching element 6 inputs the signal of the L level, and both two transistors, P channel FET and N channel FET, in the forward switching element 6 are ON. On the contrary, in the above situation, the gate electrode of the N channel FET in the inverse switching element 7 inputs the signal of a low level (L level as a level of a low voltage) and the gate electrode of the P channel FET in the inverse switching element 7 inputs the signal of the H level, both two transistors, P channel FET and N channel FET in the forward switching element 6 are OFF. In this case, the level of the voltage inputted to the selection connection terminal 8 is outputted to the common terminal 10 through the forward switching element 6.
On the other hand, when the level of the switching control signal is the L level, both the P channel FET and the N channel FET in the inverse switching element 7 are ON, so that a level of the voltage inputted to the selection connection terminal 9 is outputted to the common terminal 10 through the inverse switching terminal 10.
Next, a description will be given of the operation of the forward and inverse switching elements 6 and 7.
FIG. 4A is a diagram showing the ON resistence (a resistance between the source electrode and the drain electrode) of the P channel FET to be used in the switching element. As shown in FIG. 4A, the ON resistance of the P channel FET is decreased when the voltage between the source electrode and gate electrode is increased. The ON resistance of this P channel FET may be neglected when the voltage between the source electrode and gate electrode becomes lower than the threshold voltage of this P channel FET measured from the voltage of the high power source. FIG. 4B is a diagram showing the ON resistance (as the resistance between the source electrode and drain electrode) of the N channel FET to be used in the switching circuit. As shown in FIG. 4B, the ON resistance of the N channel FET is decreased when the voltage between the source electrode and gate electrode is increased. The ON resistance of this N channel FET may be neglected when the voltage between the source electrode and gate electrode becomes lower than the threshold voltage of this N channel FET measured from the voltage of the low power source.
FIG. 4C and FIG. 4D are diagrams showing an input voltage Vin and a composite ON resistance of both the P channel FET and N channel FET shown in FIG. 4A and FIG. 4B. That is, FIG. 4C is a diagram showing a case in which the voltage VCC of the high power source is set to a voltage that is not less than the sum voltage (VTHP+VTHN) of both the threshold voltages of the P channel FET and N channel FET. In this case shown in FIG. 4C, the range of the input voltage PFETON where the ON resistance of the P channel FET may be neglected is overlapped (namely, are continued) to the range of the input voltage NFETON where the ON resistance of the N channel FET may be neglected. Accordingly, it is possible to connect the source electrode to the drain electrode without any causing of the ON resistance of one of the P channel FET and N channel FET even if the input voltage Vin is increased in the range from the voltage GND of the lower power source to the voltage VCC of the high power source. When both the P channel FET and N channel FET are used for a switching circuit, there is an effect in which no ON resistance is generated in the voltage range from the low voltage GND of the lower power source to the high voltage VCC of the high power source. As a result, it is possible to provide the input voltage that has been inputted to the source electrode or the drain electrode of the FET to other electrode.
FIG. 4D is a diagram showing a case in which the voltage VCC of the high power source is set to a voltage that is not more than the sum voltage (VTHP+VTHN) of both the threshold voltages of the P channel FET and N channel FET. In this case shown in FIG. 4D, the range of the input voltage PFETON where the ON resistance of the P channel FET may be neglected is separated to the range of the input voltage NFETON where the ON resistance of the N channel FET may be neglected. Accordingly, the ON resistance of each of the P channel FET and N channel FET is generated at the half voltage VCC/2 of the voltage of the high power source and near voltage thereof when the input voltage Vin is changed from the low voltage GND of the low voltage power source to the high voltage VCC of the high voltage power source. As a result, the voltage inputted to the source electrode or the drain electrode is reduced by the ON resistance and the reduced voltage is outputted to other electrode.
As apparent from the foregoing explanation for the conventional switching circuit and the conventional switched capacitor filter, when the switching element performs by using the power source whose voltage is not more than the sum voltage (VTHP+VTHN) of the threshold voltages of both the P channel FET and N channel FET, the P channel FET or the N channel FET in this switching element has the ON resistance, so that it is difficult to output the input voltage as the output without decreasing of the magnitude of the input voltage.
That is, it is possible to operate switching circuits and switched capacitor filters, each of them incorporates the above switching element in the voltage that is not more than the sum voltage of the threshold voltages of both the P channel FET and N channel FET in the switching element. In addition, it is difficult to operate the conventional switched capacitor filter under the lower voltage by other factors.
We will explain this drawback of the conventional switched capacitor filter in the following concrete example.
FIG. 5 is a circuit diagram showing the internal configuration of the operational amplifier 28 incorporated in the conventional switched capacitor filter shown in FIG. 1. In FIG. 5, the reference number 35 designates an input terminal of the operational amplifier 28 to which an inverted input signal is supplied, and 48 denotes a non-inverting input transistor whose gate inputs the inverted input signal is inputted. The reference number 49 indicates a non-inverse input transistor whose gate is connected to the ground voltage and whose source is connected to the source of the inverting input transistor 48. The reference number 50 designates a current source transistor placed between the source electrodes of both the transistors 48 and 49 and the ground voltage, and for limiting the sum of currents flowing through those transistors 48 and 49.
The reference number 51 designates a first load transistor placed between the drain electrode of the inverse input transistor 48 and the high voltage power source. The reference number 52 denotes a second load transistor placed between the drain electrode of the non-inverse input transistor 49 and the high voltage power source. The reference number 36 indicates an amplifier output terminal connected to the drain electrode of the first load transistor 51. The drain electrode of the second load transistor 52 is connected to the gate electrode of the first load transistor 51.
Next, a description will be given of the operation of the operational amplifier 28.
For example, when the level of the voltage to be inputted to the input terminal 35 of the amplifier is increased, the magnitude of the current flowing between the source electrode and drain electrode in the inverting input transistor 48 is increased. Because the magnitude of the sum current between a differential current flowing through the inverting input transistor 48 and a differential current flowing through the non-inverting input transistor 49 is limited by the power source transistor 50, the magnitude of the differential current flowing through the non-inverting input transistor 49 is decreased. Accordingly, the magnitude of the current flowing through the second load transistor 52 is also decreased, so that the magnitude of the voltage in the second load transistor 52 is decreased. This results in magnitude imbalance between both the output current of the first load transistor 51 and the input current of the inverse input transistor 48, and the differential current between both the currents is provided by other circuits (omitted from FIG. 5) connected to the operational amplifier 28.
On the contrary, when the magnitude of the voltage to be inputted to the input terminal 35 of the operational amplifier is decreased, the differential current flows through the output terminal 36 in the operational amplifier 28. In the operational amplifier 28 performing the above operation, because the P channel FETs and the two N channel FETs are placed between the high voltage power source and the low voltage power source in three stages, it must be required to use a power source whose voltage is not less than the sum voltage between the threshold voltages of those three FETs. Accordingly, the conventional switched capacitor filter requires the power source whose voltage is not less than the sum of the three threshold voltages of those FETs. Therefore the conventional switched capacitor filter has the drawback that it is difficult to operate the conventional switched capacitor filter by using the power source whose voltage is not more than the sum of the threshold voltages of two FETs selected in the three FETs even if operational voltage of the current source transistor is adjusted.